As the effective width of a gate stack becomes smaller, the transistors that can be made from them become faster. However, with present line widths at 0.25 micron, or even 0.18 micron, it is increasingly difficult to anisotropically etch through various layers of a small diameter gate stack. After forming the gate stack, the source and drain are ion implanted. The extra capacitance generated when the implants overlap the source and drain, acts to slow down the transistors. Thus the width of the gate should match, not overlap, the source and drain implants.
100 Nanometer (hereinafter nm) gate lines in CMOS transistors operating at 1.2-1.5V have been described. These transistors have high drive current, reporting a 10% improvement over existing technologies, with no change in the gate oxide thickness. In part, a notched polysilicon process is used to reduce the apparent gate polysilicon dimension by introducing a notch at the polysilicon-gate oxide interface. This notch enables a reduction in the total gate capacitance by reducing the gate length dimensions at the interface to 100 nm.
Germanium devices are faster than silicon devices because the mobility of their electrons is greater, and there are more of them. Thus transistors made using a silicon-germanium gate stack are of present interest.
It would be advantageous to reduce the effective gate width of transistor gates including a layer of germanium by forming a notch at the interface between a silicon layer and a germanium layer of a gate stack. In addition, a notch at the bottom of the gate would reduce the cooling capacity.